Avoiding glitches in digital circuit?

Question

What is the best way to avoid glitches when designing a digital logic circuit? Also, does a programmable logic device output static hazards?

Answer 1

Add a 0.1 uF cap with very short leads across every IC. Add a 100uF 10v cap for every PC board.

Further precautions if you are near any motors or solenoids or relays:

Bypass every DC solenoid or relay with a reverse connected rectifier. Use RC suppression on AC solenoids, relays and motors.

Put your electronics in a shielded enclosure. Any digital inputs or outputs that have to travel long distances, use clamp diodes to + supply and ground, and use feedthrough caps to bring them outside the shielded enclosure.

"Does a PLA output static hazards"? It should just output logic levels, which are not a static hazard.

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Answer 2

I worked for a process control company for 20 years. The best way is to put a capacitor across the power supply on each I.C. The typical value is .1 mfd. Other companies do the same. Even computers all have them. That most always clears up the glitch problem. As for PAL's, i'm not sure there is static protection on the outputs. You can get data on any I.C. at  www.alldatasheet.com

Answer 3

There is only one way to avoid glitches:  make everything synchronous.  Synchronize ALL inputs to your clock before applying them to combinatorial logic inputs.  Register all outputs of your combinatorial logic.  

Using capacitors on the digital lines is only a band-aid for the problem.  You need to get rid of glitches at the source.

PLAs, PLDs, CPLDs, etc. will output static hazards if the output is combinatorial -- just like any other set of discrete gate logic.  FPGA's, too!

Synchronize!

Register, register, register!

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