CD74HC7046AE Phase Locked Loop Question ?

Question

So I have 2 square waves with a 90 degree offset flowing through this PLL (http://pdf1.alldatasheet.com/datasheet-pdf/view/27076/TI/CD74HC7046AE.html)

The square waves are equal in frequency and both have a 50% duty cycle. I was planning on using the PC2 portion of the circuit as a phase comparitor.

On page 3 of the data sheet it says the following:

[When the frequencies of SIGIN and COMPIN are equal but the phase of SIGIN leads that of COMPIN, the p-type output driver at PC2OUT is held “ON” for a time corresponding to the phase differences (φDEMOUT). When the phase of SIGIN lags that of COMPIN, the n-type driver is held “ON”. ]

My question is: What is the output for when the p-type and n-type drivers are on? I simply need a somewhat constant measurement if SigIN leads CompIN (by 90 degrees), and a different but also nearly constant measurement if the opposite condition exists.

Is this what the PC2 circuit does?

- If so, what are the outputs for both conditions?

- If not, what does it actually output? And how can I differentiate between the outputs?

Answer 1

The output out of PC2 is a variable square wave filtered to a DC level by the 2 Resistors and Capacitor connected to it.  This DC level is then fed back to control the frequency of the VCO portion of the circuit.

Figure 9 should give you an idea of what I am talking about.

Answer 2

Lemme guess - you actually want a quadrature decoder for an optical quadrature encoder?  Sounds like it from your signal description.  Anyway, pin 15 doesn't look any good for your direction detector since, because your signals are always 90 degrees apart, this pin will always be low.

But as a direction detector, it looks like the tristate pin 13 plus a Schmidt latch will do the job.  Pin 13 into a small cap.  Other side of the cap to the center of a voltage divider, say 2x10k between GND and Vcc, and to the input of a CMOS Schmidt inverter,  Output of inverter to a second inverter.  Output of second inverter has a 10k resistor, other end of resistor to input of first inverter/voltage divider for positive feedback.  Output of second inverter is direction (DIR).  Circuit willl power up with DIR low and stay low as long as COMP and SIG are either non-active or COMP leads SIG.  The voltage at the divider will be one third of Vcc.  Once SIG begins leading COMP, the p-type will go active, both inverter outputs will change state w/ voltage at divider=Vcc.  P-type goes inactive and pin 13 goes tristate once COMP is high (assuming SIG is high, if Sig is low then it's once COMP goes low), and divider goes to 2/3 Vcc, but second inverter output remains unchanged, properly indicating direction/lead/lag.

I don't mean to insult your intelligence with the excessively-descriptive details, I'm fairly certain much of it was obvious to you and you already knew perfectly well how to do a Schmidt, I was just making sure in case you didn't.

And I have to admit I didn't fully flesh it out to prove this is correct, only enough to be pretty confident.  And good idea, normally a quad decoder is done with a flock of flipflops and a couple gates.  Actually, I'd bet that somewhere someone does make a quad decoder IC, saving you one chip, take a google maybe.