How can i write a VHDL description of a 2-bit counter as a finite state machine?

Question

the 2-bit counter has several inputs clk, rst, load, enable etc. and should able to reset, accept input, count up or count down..pls help me. i don't know how..

Answer 1

Neither is this. Nor do I know what the h**l you're talking about.

I just need the two points to ask more questions.

Answer 2

this isnt an answer.. but holy c**p.. wtf r u talking about

Answer 3

Customized processors use compiler analysis and design automation techniques to take a generalized architectural model and create a specific instance of it which is optimized to a given application or set of applications. These processors offer the promise of satisfying the high performance needs of the embedded community while simultaneously shrinking design times. Finite State Machines (FSM) are a fundamental building block in computer architecture, and are used to control and optimize all types of prediction and speculation, now even in the embedded space. They are used for branch prediction, cache replacement policies, and confidence estimation and accuracy counters for a variety of optimizations. In this paper, we present a framework for automated de-sign of small FSM predictors for customized processors. Our approach can be used to automatically generate small FSM predictors to perform well over a suite of applications, tailored to a specific application, or even a specific instruction. We evaluate the use of these customized FSM predictors for branch prediction over a set of benchmarks.  

2-bit counter  diagram:

http://esd.cs.ucr.edu/labs/counter/count...

Citation:  Timothy Sherwood, Brad Calder, "Automated Design of Finite State Machine Predictors for Customized Processors," isca, p. 0086,  28th Annual International Symposium on Computer Architecture (ISCA'01),  2001