Multiplexer universality!?

Question

Hi,

How to build a AND gate using a 2X1 multiplexer?

The same for a NOT gate?

I am stuck on it!

thank you

Answer 1

I think I have a different interpretation from "s t".

I think a 2x1 mux would have 2 "data" inputs & 1 "select" input & 1 output. That is the "select" chooses which input to send to the output.

My suggestion: draw the truth tables of what you have & what you want & stare at them awhile.

Maybe it would look like inputs AB along the top

           00 01 11 10

s = 0    0  0   1   1   ie select A

s = 1    0  1   1   0  ie select B

AND should look like one input value across the top, one down the side

     0  1

0   0  0

1   0  1

If we look for the pattern we want in the mux truth table we should see it more than once, I'd guess since it's symmetrical

The first two rows look promising

           AB AB

           00  01

s = 0    0   0  

s = 1    0   1  

So if we connect one input to s "select" input & the other to the B input & set the A input to 0 we seem to get the correct truth table.

You can see in the process that I have decided that s = 1 selects the B input.  If you reverse the sense of the "s" input you have to get it right again (swap inputs?).

So the NOT should be easier.

           AB AB AB AB

           00   01 11  10

s = 0    0    0    1    1   ie select A

s = 1    0    1    1    0  ie select B

the last column seems to get me

s=0 => 1

s=1 => 0

so try set mus inputs for the last column: A=1, B=0 & connect the input to "s".

Again this should be connect the input to the "s" mux input & set the MUX input selected when s=0 to 1 & the input selected when s=1 to 0.

Hope this helps.

Answer 2

I'm assuming that by "2x1 mult" you mean a 2 bit input and 1 bit output.

since:

0*0=0

1*0=0

0*1=0

1*1=1

then I would say that an and gate IS a 2x1 multiplier, or that a 2x1 multiplier IS an and gate. But you didn't provide a lot of context so I could be confused.

An and gate can have any number of inputs greater then 1, and it has always one output.

It's output will be 1 (or "high") only when all of the inputs are high at the same time.

A not gate has a single input and a single output. The truth table is:

1=0

0=1

In other words, if you put in a 1, you get a 0, and vice versa.

Answer 3

The mux logic equation is y = (sel & a) | (~sel & b).

note... "~" means negation (C, Verilog, others.)

The AND gate.... wire b = 0, a = in1, sel = in2.

The "~sel & b" term is always false, so you're left with sel & a (that is, in1 & in2)

The NOT.... wire a = 0 and b = 1 and sel as in.

"sel & a" is always false, "~sel & b" is true only when sel (in) is false, so y = ~sel  (that is, ~in).