This part of the verilog code does not work! what's wrong with it?

Question

let A = 1, B = 64 and C=1904 for an especial case, but the output will be 0.

module PCmux( input clk, input[1:0] s, input[31:0] A, B, C, output reg[31:0] D);

always@( A or B or C or s)begin

case (s)

00: D <= A;

01: D <= B;

10: D <= C;

endcase

end

initial

begin

D = 31'b 0;

end

endmodule

Answer 1

You haven&#039;t defined s.

The case statement does not have an explicit default.

I suspect that since s is undefined, so is the case statement therefore D will be unchanged from the initial value of 31&#039;b0..

I would rewrite the case statement like this:

case (s)

00: D &lt;= A;

01: D &lt;= B;

10: D &lt;= C;

default: D &lt;= 31&#039;b 0;

endcase

altermately, since there are only 2 bits to s, you can explicitly code

11: D &lt;= 31&#039;b0;

endcase

ALSO... rather than use an &#039;initial&#039; statement to set an initial value, just set the value of D before the case statement.  &#039;Initial&#039; statements are not synthesizeable.  They are only good for simulation.

always @(A or B or C or s) begin

D = 31&#039;b0;

case (s)

...

end

Finally, if that is all the code in the module, you don&#039;t need the clk signal.

.