Why must the gate-to-source voltage of an n-channel JFET always be either 0 or negative?

Question

A Certain N-Channel JFET is biased such that Vgs = -2V. What is the value of Vgs(off) if Vp is specified to be 6V? Is the device on?

Answer 1

Since it is an N-channel (or PNP) it's reversed bias so we need the gate voltage to be at the threshold voltage / pinch-off voltage (Vt/p) to be off.

Here are the following regions for a JFET:

-- Cut-off: Vgs <= Vp

-- Triode: Vp <= Vgs <= 0, Vds  <= Vgs - Vp

-- Saturation: Vp <= Vgs <= 0, Vds >= Vgs - Vp

We can see that we are definitely in the cut-off region meaning no charge carriers are flowing because there is not enough bias to create a channel, but I think Vp = 6V means |Vp| so we would need more info on the drain voltage to know what region we are in.

The Vds (drain voltage) will be a positive bias so we need the difference at the gate to narrow the channel. Meaning the gate voltage Vgs must be no greater than 0.3V to operate.

I pasted a link of a cool site that models FETs. Enjoy!